Tentative Schedule

Day 1

S.No Time Speaker
1 Inaugural & Keynote Session 10:30 am -11:00 am
2 VLSI Technology-Importance and Role in Design 11:00 am - 12:00 pm Prof. B.R.Singh
Tea Break~ 12:00 pm - 12:15 pm
3 SRAM Design and Memory Architecture 12:15 am - 1:45 pm Mr. Sumit Srivastava ( Synopsys)
Lunch ~ 1:45pm – 2:50pm
4 SRAM Design and Memory Architecture 2:50 pm - 4:00 pm Mr. Sumit Srivastava ( Synopsys)
5 Lab session 4:00 pm -6:00 pm Dr. Manish Goswami,
Dr. Prasanna Kumar Misra

Day 2

S.No Time Speaker
1 Design of CMOS analog sub circuits 9:00 am -10:00 am Dr. Manish Goswami
2 Design techniques for VLSI system design 10:00 am - 11:00 am Dr. Prasanna Misra
Tea Break~ 11:00 am -11:15 am
3 Low Power Design Techniques 11:15 am - 1:15 pm Dr. Prasanna Misra
Lunch ~ 1:15pm – 3:00pm
4 VLSI system design –Lab 3:00 pm -6:00 pm Dr. Manish Goswami

Day 3

S.No Time Speaker
1 Design of CMOS analog sub circuits 9:30 am -11:00 am Dr. Manish Goswami
Tea Break~ 11:00 am -11:15 am
2 Aspect of functional verification in a complex system on chip 11:15 am-1:15 pm Mr. Nitin Jaiswal (NXP Semiconductor)
Lunch ~ 1:15pm – 2:45pm
3 Aspect of functional verification in a complex system on chip 2:45 am - 3:30 pm Mr. Nitin Jaiswal (NXP Semiconductor)
4 Lab session 3:30 pm - 7:00 pm Dr. Prasanna Misra

Day 4

S.No Time Speaker
1 VLSI System design, testing, verification etc. 9:30 am - 11:00 am Mr. Surendra Tadi (Qualcomm)
Tea Break~ 11:00 am -11:15 am
2 Feedback and Valedictory 11:15 am - 1:00 pm -
Lunch ~ 1:15pm – 2:30pm